1. Field of the Invention
The present invention relates to a dynamic random access memory device (DRAM) and, more particularly, to a synchronous DRAM operating in synchronous with a clock signal supplied thereto.
2. Description of the Related Art
In order to has a DRAM operates at more higher speed, a synchronous DRAM has been developed and put into practical use. The synchronous DRAM operates in synchronism with a clock signal supplied thereto from a microprocessor, a microcomputer or a microcontroller (called collectively a "CPU). The CPU also supplies the synchronous DRAM with a data-read command or a data-write command. In response thereto, the DRAM operates to read or write data from or into a selected memory cell or cells in synchronism with the clock signal.
As well known in the art, a refresh operation is also necessary for the synchronous DRAM to prevent the destruction of data stored in each memory cell. The CPU is therefore required to further issue a refresh request command to the synchronous DRAM. In response to this command, the synchronous DRAM initiates a refresh operation in which one word line is selected by the content of an internal refresh address counter and the memory cells connected to the selected word lines are refreshed.
It is to be noted here that a cycle of issue of the refresh request command is standardized to be 15.625 .mu.sec. In other words, the refresh request command is issued by the CPU every 15.625 .mu.sec. The synchronous DRAM thus performs the refresh operation in such a manner as described above.
Referring to FIG. 1, a synchronous DRAM 1 is coupled to a CPU 1 to receive a clock signal CLOCK. The CPU 1 supplies a data-write or a data-read command to the DRAM 2 in synchronism with the clock signal CLOCK. The command thus supplied is decoded by a command decoder 3 which then produces and supplies decoded information 31 to an internal control circuit 4. The DRAM 2 is thus brought into a desired operation controlled by a set of internal control signals 41 form the circuit 4. The CPU 1 further supplies address signals A0 to An an address buffer 6 to designate a memory cell which is to be subject to the desired operation. A row decoder 7 receives row address information and a column decoder 8 receives column address information from the address buffer 6. As a result, one of word lines WL and one of bit lines BL in a memory cell array 16 are selected to designate one of memory cells 13, Note that in the drawing, only one word line, only one bit line and only one memory cell are shown. A sense-amplifier/multiplexer circuit 9 is further activated, so that data stored in the memory cells connected to the selected word lines are applied and then restored thereinto.
When the command from the CPU 1 is a data-read mode, the selected memory cell is coupled through the multiplexer circuit 9 to a data output buffer 11. The data stored in the selected memory cell is thus read out as an output data Dout.
In the case of the data-write command being supplied, an input data Din is written into the selected memory cell by a data input buffer 10.
When the CPU issues a refresh request command in synchronism with the clock signal, as shown in FIG. 2, the command decoder 3 decodes this command and supplies a refresh request signal RF to the internal control circuit 4 and further to refresh control circuit 5. In response to the change of the refresh request signal RF to the active high level, the refresh control circuit 5 operates to transfer the content of an internal refresh address counter 12 to the row decoder 7. On the other hand, the control circuit 4 produces the set of internal control signals 41 for a refresh operation. As a result, one of the word lines WL is selected by the row decoder 7 in response to the content of the internal address counter 12 and driven by a driver 14, as shown in FIG. 2. Further, the sense amplifier circuit 9 is activated to thereby refresh the memory cells coupled to the selected word line Wi.
The control circuit 4 has an S-R flip-flop 42 which is brought into a set state by the refresh request signal RF. A refresh mode signal RFMD is thereby changed to the high level, as shown in FIG. 2. The high level of the signal RFMD prevents the command decoder 3 from responding to a command issued later from the CPU 1.
When a period of time required to perform the refresh operation has been elapsed, the refresh control circuit 5 changes a refresh end signal RFEND to the high level, as shown in FIG. 2. In response thereto, the content of the address counter 12 is updated. In response further to the signal RFEND, the control circuit 4 stops producing the refresh control signals 41 to change the selected word line WLi to the non-selection (low) level, and then produces a set of signals 41 to bring the memory circuit to a reset-precharge state. The circuit 4 further produces a precharge end signal PREND upon completion of the reset-precharge state. The flip-flop 42 is thereby reset to change the refresh mode signal RFMD to the low level, as shown in FIG. 2. The command decoder 3 is thus allowed to respond to a command from the CPU 1.
Thus, in response to one refresh command, one refresh operation is performed to select one of word lines and refresh the memory cells connected to the selected word line.
The memory capacity, i.e. the number of memory cells, of the DRAM has been increasing more and more. In accordance therewith, the size of each cell is shrunk to remarkably shorten its data holding time indicative of a time period during which the memory cell retains the data therein.
On the other hand, the synchronous DRAM receives the refresh request command in the standardized cycle as described above. For this reason, it becomes difficult that all the memory cells are refreshed at least once within the data holding time.